1. Field of the Invention
The present invention relates in general to a process for fabricating high voltage semiconductor devices. In particular, the present invention relates to a process for fabricating semiconductor devices capable of handling high voltages and large currents.
2. Technical Background
Semiconductor devices, such as, rectifiers and thyristors, are capable of withstanding up to 1,000 volts at their terminals when reverse biased, i.e., they are turned off (non-conducting). Over 100 amperes of DC current can be passed through these devices when forward biased, i.e. they are turned on (conducting). These power electronic devices are basic components of modern power control equipment. They play the role of electronic switches, corresponding to their mechanical counterparts, while enjoying generally high power handling efficiencies.
In order for these semiconductor electronic devices to handle voltages in the range of 10.sup.3 volts or higher, the junction voltage distribution profile over the terminal junction must be carefully controlled. Uneven distribution of this junction voltage may easily result in flashover or channeling in the junction area.
Referring now to FIGS. 1 to 5, a prior art process for making such devices will now be described. Semiconductor substrate 10 comprises a N.sup.+ region 12, a N- region 14 and a P.sup.+ region 16, typically prepared by epitaxially growing region 14 on initial substrate 12 and thereafter creating region 16 by further epitaxial growth or doping. Substrate 10 has thickness 13 of typically about 690 .mu.m (27 mils), N.sup.- region 14 has thickness 15 of about 110 .mu.m and P.sup.+ doped region 16 has thickness 17 of about 10 .mu.m.
Grooves 22 of depth 24 are formed in substrate 10, for example, by sawing or by etching through openings 20 in mask 18. Such methods are well known in the art. This provides the structure shown in FIG. 2. These grooves cross in both directions--as in a grid like pattern--so that the resulting device is square. The mask 18 is then removed.
A second mask 26 having openings 28 is then applied to the surface of the structure of FIG. 2. A further etching is carried out to deepen grooves 22 to penetrate into the N.sup.+ region 12. Openings 28 are generally wider than openings 20 so that stepped sidewalls are formed, resulting in grooves 30 of depth 32, as illustrated in FIG. 3.
Passivation material 36, as for example a glass or organic polymer, is spun on or otherwise applied and patterned as shown in FIG. 4 using means well known in the art to cover the sidewalls of grooves 30. This passivation material protects the PN junction formed between N.sup.- region 14 and P.sup.+ region 16 that extends to the sidewalls of grooves 30. Metal layers 38 and 39 are also formed using well known means to provide ohmic contact to the semiconductor regions. Substrate 10 is then separated into individual device die 11 by conventional means, as for example sawing or etching, to provide the finished device illustrated in FIG. 5.
In this conventional fabrication process for power semiconductors, shown in FIGS. 1-5, at least four photolithography procedures are required. They are required in each of the process stages depicted in FIGS. 2-4, respectively, namely for delineating grooves 22, grooves 30, passivation material 36 and metal 38. The precision of the results of photolithography procedures is influenced by terrain elevational fluctuations, particularly drastic elevational changes in a small substrate surface, that is, in the wafer surface areas. This is due to the limited depth of focus of the optical equipment used in the photolithography procedures.
Photolithography techniques employed in conventional semiconductor device fabrication procedures, are based on considerations of life expectancy and resolution limitations of the masks, and typically include projection scanning, reduction step-and-repeat projection aligning, and non-reduction step-and-repeat projection aligning techniques. The depth of focus is about .+-.6 .mu.m for projection, is about .+-.5 .mu.m for non-reduction step-and-repeat projection aligning, and is much smaller for the reduction step-and-repeat projection aligning. The thickness of the P.sup.+ region 16, however, as seen in FIGS. 1-5 is already 10 .mu.m, a scale which really tests the manufacturing tolerances of such techniques. As a result, the photolithography precision will be worse than barely acceptable in regions such as at the bottom of the groove 20, and/or the bottom of groove 30. Poor masking precision results in decreased fabrication yields, which leads directly to higher manufacturing costs for these semiconductor devices. Poor masking precision due to mask misalignment, on the other hand, results in poor symmetry in the formation of stepped sidewall, which in turn causes an uneven voltage distribution profile in the device and causes decreased effectiveness and premature failure of the semiconductor device.
Moreover, long etching times are required to form the deep grooves 22 and 33, hence the cost of manufacture is high. And since the grooves typically cut into the layer 12 of the substrate 10 that significantly reduces the mechanical strength of the substrate 10, breakage of the substrate will easily occur during fabrication. Thus, the conventional process of fabricating high-voltage devices cannot not gain a good fabrication yield.